1. Field of the Invention
The present invention relates to an ESD (electrostatic discharge) detection circuit and related method, and more particularly, to an ESD detection circuit and related method capable of reducing a size of the ESD detection circuit itself and extending a duration of discharge.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art ESD protection circuit 10. The ESD protection circuit 10 includes a low-pass filter 11 having a resistor R and a capacitor C, an inverter 12, and an ESD Clamp Circuit 13. The inverter 12 is composed of a P-type field effect transistor (FET) MP and a N-type FET MN. When an electrostatic signal Sesd rises at a first node Na of the ESD protection circuit 10, a voltage level at a second node Nb is temporarily maintained at a lower level because of the low-pass filter 11. The P-type FET MP is turned on and the N-type FET MN is turned off. Accordingly, through the P-type FET MP, the electrostatic signal Sesd is converted into a current signal I_trig, which is utilized for triggering the ESD clamp circuit 13 to perform a discharge operation upon the electrostatic signal Sesd at the first node Na. However, when the voltage level at the first node Na is higher than that of a normal supply voltage VDD (e.g. the voltage level at the first node Na equals 3*VDD), gate-oxide layers of the capacitor C, the P-type FET MP, and the N-type FET MN will be damaged since voltage drops across the gate-oxide layers will become much larger. In summary, the ESD protection circuit 10 cannot absorb the electrostatic signal Sesd which has greater voltage amplitudes. Further description is detailed in US patent application pub. No. 20030076636A1.
In addition, according to U.S. Pat. No. 5,956,219, another ESD protection circuit is disclosed. Although the ESD protection circuit is able to absorb an electrostatic signal having greater voltage amplitudes, this ESD protection circuit implemented by a triple well process has some disadvantages. The ESD protection circuit increases cost of production and complicates the gate-driven technique, especially when an advanced nano-scale CMOS (Complementary Metal-Oxide-Semiconductor) process is applied.
Additionally, according to U.S. Pat. No. 6,954,098, an ESD protection circuit is further disclosed. Similarly, the ESD protection circuit is also capable of absorbing an electrostatic signal having greater voltage amplitudes. In addition to a normal supply voltage, however, this ESD protection circuit further requires a lower supply voltage for proper operation. If either one of the normal or lower supply voltages is not provided, gate-oxide layers of FETs within the ESD protection circuit could be damaged. Consequently, in order to avoid the above-mentioned problems, the ESD protection circuit disclosed by U.S. Pat. No. 6,954,098 is usually implemented by the thicker gate-oxide layer process technique, subsequently increasing cost of production.